Demand for high efficiency, low cost solar cells has led to strong interest in cost-effective process technologies for forming thick (1 μm to 40 μm) layers of single crystal silicon. High temperature chemical vapor deposition (CVD) processes (on the order of 750° C.-950° C. or greater) can deposit epitaxial Si at a rate of 1-3 μm/min. Such high rate epitaxial (HRE) CVD processes can be used in a variety of solar cell fabrication schemes. For example, HRE-CVD Si layers have been deposited on (i) seed layers of super-large-grained (e.g., grain sizes on the order of 10 μm to 50 μm or greater) polycrystalline Si (poly-Si) and (ii) seed layers produced from and/or formed on porous Si, as has been described by K. Snoeckx et al. in “The potential of thin-film crystalline solar cells,” http://www.semiconductor.net/article/CA6445466.html, and G. Beaucarne and J. Poortmans in “Crystalline Si solar cells,” http://www.imec.be/wwwinter/mediacenter/en/SR2003/scientific_results/research_imec/2—4_pho to/2—4—2/2—4—2—1_cont.html?reload_coolmenus.
There is also a potential need for thick layers (on the order of 1 μm to 40 μm) of single crystal silicon on insulator (thick SOI) for high power device applications. Epitaxial growth of thick Si layers on conventional thin (150 nm to 200 nm) SOI by CVD is expected to be slow and expensive, and requires special cleaning of the initial thin SOI growth surface to ensure good epitaxy. However, the alternatives are unattractive: donor wafer bonding to a handle wafer followed by donor wafer etchback sacrifices the entire donor wafer, and the hydrogen ion implantation processes typically used for SmartCut™-type splittings are typically restricted to relatively shallow depths (e.g., a few hundred nm at most).
There is also interest in cost-effective methods for forming large-grained poly-Si films that may be used in place of currently used metal-induced crystallization (MIC) methods. While MIC methods can result in large Si grains, the intragrain defect density is high and the resulting poly-Si typically has high levels of metallic contamination. Even when metallic contamination is not present, inadequately passivated grain boundaries can reduce minority carrier lifetimes. While annealing in the presence of hydrogen molecules, radicals, and ions is often suggested as a method of passivating grain boundaries, the benefits provided by such passivation are often transient, as the hydrogen passivation is not stable to the thermal stresses of processing.
It would therefore be desirable to have alternative methods of forming thick layers of high quality single crystal Si, multicrystal Si, and large-grained well-passivated poly-Si that do not have the aforementioned limitations and disadvantages.